Semiconductor device and display apparatus

ABSTRACT

A semiconductor device for individually controlling an element to be driven, such as an electroluminescence element, includes a switching TFT which operates when a selection signal is applied to its gate and which also captures a data signal, and an element-driving TFT in which its drain is connected with a drive power source, its source is connected with the element to be driven, gate receives a data signal supplied from the switching TFT, for controlling electric power supplied from the drive power source to the element to be driven. The semiconductor device further includes a storage capacitor having a first electrode connected with the switching TFT and with the gate of the element-driving TFT and a second electrode connected between the source of the element-driving TFT and the element to be driven, for holding the gate-source voltage of the element-driving TFT in accordance with the data signal, and a switching element for controlling the potential of the second electrode of the storage capacitor. With such a configuration, all the above-described switches can be formed by TFTs of the same conductivity type and reliable supply of electric power to the element to be driven can be assured.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a circuit configuration for controllingan element to be driven, such as an electroluminescence display element.

2. Description of Related Art

Electroluminescence (EL) display apparatuses using, as an emissiveelement, a self-emissive EL element in each pixel are advantageous inthat they are self-emissive, are thin, and consume a small amount ofpower. Therefore, EL display apparatuses have attracted interest andhave been studied as potential replacements for display apparatuses suchas CRT or LCD displays.

In particular, there is anticipation that active matrix EL displayapparatuses in which a switching element, such as a thin film transistor(TFT), for individually controlling the EL element is provided for eachpixel to thereby control the EL element for each pixel will becomeavailable as high resolution display apparatuses.

FIG. 1 illustrates a circuit configuration of each pixel in an activematrix (including m rows and n columns) EL display apparatus. In the ELdisplay apparatus, on a substrate, a plurality of gate lines GL extendin the row direction and a plurality of data lines DL and drive powersource lines VL extend in the column direction. Each pixel includes anorganic EL element 50, a switching TFT (first TFT) 10, a TFT (secondTFT) 21 for driving the EL element (hereafter referred to as anelement-driving TFT) and a storage capacitor Cs.

The first TFT 10 is connected with the gate line GL and the data lineDL, and turns ON when a gate signal (a selection signal) is applied tothe gate electrode of the TFT 10. At this time, a data signal suppliedto the data line DL is stored in the storage capacitor Cs which isconnected between the first TFT 10 and the second TFT 21. A voltage inaccordance with the data signal, supplied via the first TFT 10, isapplied to the gate electrode of the second TFT 21, which then suppliesa current in accordance with the applied voltage value from the powersource line VL to the organic EL element 50. In the organic EL element50, holes injected from the anode and electrons introduced from thecathode are recombined in the emissive layer, to thereby excite emissivemolecules. Through the process in which these emissive molecules exciteuntil deactivation, the organic EL element 50 projects light. Theemission brightness of the organic EL element 50 is substantiallyproportional to the current supplied to the organic EL element 50.Therefore, by controlling the current to be supplied to the organic ELelement 50 in accordance with a data signal for each pixel as describedabove, the organic EL element is caused to emit light of a brightnesscorresponding to the data signal, so that a desired image is displayedby the display apparatus as a whole.

In such an organic EL display apparatus, in order to achieve highdisplay quality, it is necessary to cause the organic EL element 50 toreliably emit light at a brightness corresponding to a data signal.Accordingly, for the active matrix type EL display apparatus, it isrequired that the drain current does not change in the second TFT 21which is disposed between the drive power source line VL and the organicEL element 50, even when the anode potential of the organic EL element50 changes due to a current flowing through the EL element 50.

For this reason, as shown in FIG. 1, for the second TFT 21 is oftenadopted a p-channel TFT in which the source is connected with the drivepower source line VL, the drain is connected with the organic EL element50 on the anode side, and the source-drain current can be controlled bya potential difference Vgs between the source and the gate to which avoltage in accordance with a data signal is applied.

When a p-channel TFT is employed as the second TFT 21, however, there isa problem that a voltage change of the drive power source line VL causesa change in the emission brightness of each element 50, because in thep-ch TFT the source is connected with the drive power source line VL andthe drain current, namely a current to be supplied to the organic ELelement 50, is controlled by a potential difference between the sourceand the gate, as described above. Because the organic EL element 50 is adriven-by-current type element as described above, when a bright imageis displayed for a certain frame period (when, for example, a largewhite area is displayed), for example, a great amount of current flowsat a time from a single drive power source Pvdd to a large number oforganic EL elements 50 on the substrate via the corresponding drivepower source lines VL, and the potential of these drive power sourcelines VL changes. Further, in a region which is far from the drive powersource Pvdd and has a significant voltage drop due to line resistance ofthe drive power source line VL, such as in a pixel positioned distantfrom the power source, the drive power source line VL at a low voltageresults in the emission brightness of each organic EL element 50 beinglower than that of elements located closer to the power source.

In addition, when a p-ch TFT is used as the second TFT 21, it isnecessary to reverse the polarity of a data signal to be supplied to thesecond TFT 21 with regard to the polarity of a video signal, and thusnecessary to provide a polarity reverse means in the driver circuit.

SUMMARY OF THE INVENTION

In order to solve the above problems, an object of the present inventionis to ensure that electric power supplied from the drive power sourceline to the element to be driven is unaffected by the voltage change ofthe drive power source.

Another object of the present invention is to match the polarity of adata signal supplied to the element-driving thin film transistor withthe polarity of a video signal, to thereby simplify a drive circuit.

In order to achieve the foregoing objects, in accordance with one aspectof the present invention, there is provided a semiconductor devicecomprising a switching thin film transistor which operates when aselection signal is applied to gate and also captures a data signal; anelement-driving thin film transistor a drain of which is connected witha drive power source connected with the element to be driven, said gatereceiving a data signal supplied from the switching thin filmtransistor, for controlling electric power supplied from the drive powersource to the element to be driven; a storage capacitor having a firstelectrode connected with the switching thin film transistor and with thegate of the element-driving thin film transistor and a second electrodeconnected between the source of the element-driving thin film transistorand the element to be driven, for holding a gate-source voltage of theelement-driving thin film transistor in accordance with the data signal;and a switching element for controlling a potential of the secondelectrode of the storage capacitor.

In accordance with anther aspect of the present invention, there isprovided an active matrix display apparatus including a plurality ofpixels arranged in a matrix, in which each pixel comprises at least anelement to be driven; a switching thin film transistor which operateswhen a selection signal is applied to gate and also captures a datasignal; an element-driving thin film transistor in which a drain isconnected with a drive power source, a source is connected with theelement to be driven, and a gate receives a data signal supplied fromthe switching thin film transistor, for controlling electric powersupplied from the drive power source to the element to be driven; astorage capacitor having a first electrode connected with the switchingthin film transistor and with the gate of the element-driving thin filmtransistor and a second electrode connected between the source of theelement-driving thin film transistor and the element to be driven, forholding a gate-source voltage of the element-driving thin filmtransistor in accordance with the data signal; and a switching elementfor controlling a potential of the second electrode of the storagecapacitor.

As described above, because a voltage between the gate and the sourceconnected with the element to be driven, of the element-driving thinfilm transistor (also referred to as a gate-source voltage) is held bythe storage capacitor, it is possible to supply a current in accordancewith a data signal to the element to be driven, even when the element tobe driven is activated and the source potential of the element-drivingthin film transistor connected to the driven element is increased, andan n-channel (n-ch) thin film transistor can be used as theelement-driving thin film transistor. Further, as the power supply tothe element to be driven is unlikely to be affected by a voltage changein the drive power source line, stability of the power supply can beassured.

Preferably, the n-channel thin film transistor includes an LD region inwhich a low concentration of impurities is doped between a channelregion and each of source and drain regions in which a highconcentration of impurities is doped.

In particular, the LD region of this driving transistor is preferablymade larger than the LD region of n-channel transistor at least in aperipheral circuit, and is preferably larger than the LD region of theswitching transistor.

Consequently, accuracy of adjustment of the current amount with respectto a change in the voltage applied to the gate can be increased withoutincreasing the transistor. Further, because the space required forlayout of the transistor is reduced, increased brightness as a result ofincreased aperture ratio and reduction in the power consumption can bothbe achieved.

In accordance with another aspect of the present invention, the elementto be driven is an electroluminescence element. Because the brightnessof light emitted by an electroluminescence element corresponds to thesupplied current, for example, it is possible to cause each element toemit light at brightness in accordance with a data signal by supplying acurrent in the circuit configuration described above.

In accordance with still another aspect of the present invention, theswitching element controls the potential of the second electrode of thestorage capacitor in accordance with the switching ON and OFF of theswitching thin film transistor.

In accordance with a further aspect of the present invention, theswitching element controls the second electrode of the storage capacitorat a fixed potential when the switching thin film transistor is ON.

In accordance with a still further aspect of the present invention, theswitching element controls the second electrode of the storage capacitorat the fixed potential before the switching thin film transistor isturned ON, and stops the potential control for the second electrode ofthe storage capacitor after the switching thin film transistor is turnedOFF.

In accordance with another aspect of the present invention, theswitching element is a thin film transistor and controls the potentialof the second electrode of the storage capacitor in accordance with apredetermined reset signal or a selection signal supplied to theswitching thin film transistor.

By controlling the potential of the second electrode of the storagecapacitor under control of the switching element as described above, itis possible to reliably and easily accumulate a charge in accordancewith a data signal in the storage capacitor and maintain the gate-sourcevoltage of the element-driving transistor for a predetermined period.

In accordance with another aspect of the present invention, theswitching element is connected with the source of the element-drivingthin film transistor and is used for discharging, at predeterminedtiming, a charge accumulated in the element to be driven.

According to the present invention, because the switching elementconnected to the element to be driven is provided in each pixelcorresponding to each element to be driven, it is possible to reliablyand simply discharge the element to be driven through the switchingelement, and therefore without providing any additional element for thispurpose.

In accordance with another aspect of the present invention, theswitching element is connected with the source of the element-drivingthin film transistor and is used for measuring the source potential orcurrent of the element-driving thin film transistor connected to theelement to be driven.

Because the switching element which is formed by a thin film transistor,for example, is connected with the source of the element-driving thinfilm transistor, by controlling the switching element ON, the sourcepotential or current of the element-driving thin film transistor can bedetected through the switching element. It is therefore possible toperform such a measurement in order to verify, before use, an estimatedamount of current to be supplied to the element to be driven.

Further, the present invention provides an organic EL display apparatusincluding a plurality of electroluminescence elements arranged in amatrix, in which a driving transistor is provided corresponding to eachelectroluminescence element for controlling a drive current to besupplied to the electroluminescence element, and the driving transistoris an n-ch transistor and includes an LD region in which a lowconcentration of impurities is doped between a channel region and eachof source and drain regions in which a high concentration of impuritiesis doped. In particular, it is preferable that the LD region of thedriving transistor is larger than the LD region at least in a peripheraltransistor.

By providing such a large LD region, it is possible to control a currentto be supplied to the electroluminescence element with high accuracywhile securing a high aperture ratio.

It is also preferable that the gate of the driving transistor isconnected with the switching transistor and one end of the capacitor, aconnection point of the electroluminescence element and the drivingtransistor is connected to a low voltage power source via the dischargetransistor, and the connection point of the electroluminescence elementand the driving transistor is also connected to other end of thecapacitor.

As described above, according to the present invention, it is possibleto reliably supply electric power to an element to be driven such as anelectroluminescence element.

Further, a data signal used for operating the element to be driven canbe generated and used without the need, for example, for reversing thepolarity with regard to a video signal in a display apparatus.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other objects of the invention will be explained in thedescription below, in connection with the accompanying drawings, inwhich:

FIG. 1 is a view showing a circuit configuration of an active matrixtype organic EL display apparatus of a prior art;

FIG. 2 is a view showing an exemplary configuration of a circuit,corresponding to one pixel, for driving an organic EL element, inaccordance with an embodiment of the present invention;

FIGS. 3A and 3B are views showing an exemplary configuration of acircuit for generating a gate signal and a reset signal to be suppliedto each pixel in accordance with the present invention;

FIG. 4 is a timing chart showing an operation of the circuit shown inFIGS. 3A and 3B;

FIG. 5A is a view showing another circuit configuration, correspondingto one pixel, for driving an organic EL element, in accordance with theembodiment of the present invention;

FIG. 5B is a view showing still another circuit configuration,corresponding to one pixel, for driving an organic EL element, inaccordance with the embodiment of the present invention;

FIG. 6 is a plan view corresponding to one pixel having the circuitconfiguration shown in FIG. 5A;

FIGS. 7A, 7B, and 7C are cross sectional views taken along lines A-A,B-B, and C-C, respectively, of FIG. 6;

FIG. 8 is a plan view corresponding to one pixel having the circuitconfiguration shown in FIG. 5B;

FIG. 9 is a view showing an exemplary configuration of a TFT having anLD structure;

FIG. 10 is view showing an exemplary configuration of a TFT having anenlarged LD region;

FIG. 11 is a view showing another exemplary configuration of a circuitfor generating a gate signal and a reset signal to be supplied to eachpixel in accordance with the present invention; and

FIG. 12 is a view showing still another exemplary configuration of acircuit for generating a gate signal and a reset signal to be suppliedto each pixel in accordance with the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Preferred embodiments of the present invention will be described withreference to the drawings.

FIG. 2 shows a configuration of a circuit for driving an organic ELelement in accordance with one embodiment of the present invention. Inthis example, specific description will be provided using a circuitconfiguration corresponding to one pixel of an active matrix organic ELdisplay apparatus, as shown in FIG. 2.

Referring to FIG. 2, within one pixel, an organic EL element 50 whichacts as an element to be driven or a display (pixel) element, aswitching thin film transistor (first TFT) 10, an element-driving thinfilm transistor (second TFT), and a resetting thin film transistor(third TFT) 30 which serves as a switching element used for resetting,are provided.

The first TFT 10 is formed by an n-channel TFT in this example. In thisfirst TFT 10, a gate electrode is connected with a gate line GL, a drainis connected with a data line DL, and a source is connected with thesecond TFT 20 and with a storage capacitor Cs, as will be furtherdescribed.

In the second TFT 20, which is formed by an n-ch TFT in this embodiment,the drain is connected with a drive power source Pvdd (which is actuallya drive power source line VL in this example), and the source isconnected with the organic EL element on the side of an anode. Further,a gate of the second TFT 20 is connected to the source of the first TFT10 and also with a first electrode of the storage capacitor Cs, whichwill be described below.

The storage capacitor Cs has the first electrode which is connected tothe source of the first TFT 10 and the gate of the second TFT 20, and asecond electrode which is connected between the source of the second TFT20 and the anode of the organic EL element 50.

The third TFT (discharging transistor) 30 is also formed by an n-ch TFT(though it may be a p-ch TFT). In this third TFT 30, gate is connectedwith a reset line RSL to which a reset signal is to be applied, thedrain is connected with the second electrode of the storage capacitorCs, and the source is connected with a capacitor line SL to which avoltage for defining the second electrode potential of the storagecapacitor Cs is supplied.

In the circuit configured as described above, the first TFT 10 turns ONin response to a selection signal (a gate signal) applied to the gateline GL. The third TFT 30 is controlled ON or OFF at substantially thesame timing as the ON-OFF control of the first TFT 10. Therefore, whenthe first TFT 10 turns ON, the third TFT 30 is also turned ON by a resetsignal, and the second electrode of the storage capacitor Cs has apotential which is equal to a fixed potential Vsl (e.g. 0V) of thecapacitor line SL connected with the third TFT 30. Thus, when the firstTFT 10 turns ON and the source voltage of the first TFT 10 becomes equalto the voltage of a data signal supplied to the data line DL, thestorage capacitor Cs is charged in accordance with a difference betweenthe fixed potential of its second electrode and the source potential ofthe first TFT 10, which is substantially a voltage corresponding to adata signal.

When the second TFT 20 is switched ON by application of a voltage inaccordance with a charge held on the storage capacitor Cs onto the gateof the second TFT 20, a current in accordance with the gate voltage ofthe second TFT 20 is supplied to the organic EL element 50 from thedrive power source line VL through the drain-source of the second TFT20. Consequently, the source potential of the second TFT 20 is increasedin accordance with an amount of current flowing therethrough. At thistime, the third TFT 30 is controlled OFF, so that the second electrodeof the storage capacitor Cs is disconnected from the capacitor line SL.This causes the storage capacitor Cs to be connected between the gateand source of the second TFT 20, in which state an increase in thesource potential causes a corresponding increase in the gate potential,and the gate-source voltage Vgs of the second TFT 20 in accordance witha data signal is maintained by the storage capacitor Cs.

According to the circuit configuration of the present embodiment, asdescribed above, even when current flows through the organic EL element50 to thereby increase the source potential of the second TFT 20,constant supply of a current in accordance with a data signal to theorganic EL element 50 can be ensured by the function of the storagecapacitor Cs. Further, as an n-ch TFT is employed as the second TFT 20,a data signal having the same polarity as that of a video signal can beused. Moreover, because the drive power source Pvdd to which the drainof the second TFT 20 is connected has a sufficiently high voltage suchas 14V, it is possible to drive the second TFT 20, which is an n-ch TFT,in its saturated region, so that the organic EL element 50 can besupplied with a current independent from a change in the source-drainvoltage. It should be noted that each circuit element can be driven,with a gate signal which is supplied to the gate line GL being in arange of, for example, 0V to 12V, a data signal being 1V to 6V, and thefixed potential of the capacitor line SL being approximately 0V.

Further, as will be described later, the n-ch second TFT 20 may adopt aso-called LDD structure (which will be referred to as an LD structure inthe present specification) having a region in which a low concentrationof impurities are doped, between the channel and each of the drain andsource.

FIGS. 3A and 3B schematically show a circuit for supplying a gate signal(G1˜Gm) and a reset signal (RS1˜RSm) corresponding to each pixelconfigured as described above, and FIG. 4 shows the operation of thecircuit shown in FIGS. 3A and 3B. In an active matrix organic EL displayapparatus, the first TFTs 10 in each of the pixels arranged in a matrixis sequentially selected for each row (for each gate line GL) by a gatesignal output from a vertical driver which is schematically shown inFIGS. 3A and 3B, and a data signal on the corresponding data line DLwhich is output from a horizontal driver (not shown) is captured.

A shift register 110 of the vertical driver 100 shifts a vertical startpulse at every 1H (one horizontal scanning period), and sequentiallyoutputs a shift pulse S1, S2, S3. Sm to the output section 120.

The output section 120 is configured, for example, as shown in FIG. 3B.Specifically, the output section 120 has two AND gates 122 and 124corresponding to each row for sequentially outputting a gate signal G1,G2, G3 . . . Gm and a reset signal RS1, RS2, R3 . . . Rsm to thecorresponding line. The AND gate 122 performs logical AND operation ontwo shift pulses which are successive with respect to time sequence. Toone input end of the AND gate 124, an enable signal ENB (see FIG. 4)which inhibits a gate signal from being output to the gate line issupplied at a switching period of 1 H. Therefore, the AND gate 124performs logical AND operation on this ENB and the output of the ANDgate 122. The logical product of the two shift pulses (which are S1 andS2 in the example of FIGS. 3A and 3B) output from the AND gate 122 isused as a reset signal RS (which is RS1 in Fig. FIGS. 3A and 3B) in thisembodiment. The AND gate 124 outputs a result of the above-describedlogical AND operation as a gate signal (which is G1 in FIGS. 3A and 3B)to each gate line GL, only at a period in which output of the AND gate124 is enabled by an ENB signal.

The reset signal RS output from the AND gate 122 is applied to the gateof the third TFT 30 of a corresponding pixel via the rest line RSL, asdescribed above, and the gate signal is applied to the gate of the firstTFT 10 of the corresponding pixel. Here, the reset signal RS and thegate signal G generated by the circuit shown in FIGS. 3A and 3B has arelationship as shown in FIG. 4. Specifically, as can be seen from thecomparison of G1 and RS1 applied to the pixel at the first row, forexample, the H level period of the gate signal G (ON control period forthe n-ch TFT 10) is shorter than the H level period of the reset signalRS (ON control period for the n-ch TFT 30) by a period which is limitedby the ENB signal.

Accordingly, in an example case of the pixel at the first row which iscontrolled by G1 and RS1, the third TFT 30 is first turned ON by thereset signal RS1. After the second electrode of the storage capacitor Csis fixed to the potential of the storage capacitor line, the first TFT10 turns ON by the gate signal G1, and a voltage which is substantiallythe same as that of data signal on the data line DL is applied to thefirst electrode of the storage capacitor Cs. Then, after the gate signalG reaches L level (TFT OFF level), the RS signal comes to the L level.Namely, the second electrode of the storage capacitor Cs is maintainedat the fixed potential Vsl until the first TFT 10 turns OFF and thepotential of the first electrode is determined. It is therefore possibleto reliably prevent the problem that the first electrode potential ofthe storage capacitor Cs changes by turning the third TFT 30 OFF whenthe first TFT 10 is ON, to thereby cause the data signal once held onthe data line DL to be leaked through the first TFT 10 which is ON.

FIGS. 5A and 5B show another circuit configurations corresponding to onepixel which can be employed in the present embodiment. It should benoted that elements in FIGS. 5A and 5B which are common to those in FIG.2 are denoted with the same reference numerals and will not be describedagain below.

The circuit configuration of FIG. 5A differs from that in FIG. 2 only inthat a plurality of (two, in this example) n-ch TFTs are provided inparallel between the drive power source line VL and the organic ELelement 50, and operates in the same manner as the circuit of FIG. 2.With such a configuration including a plurality of (k) second TFTs 20connected in parallel, when a current i equally flows in each second TFT20, a total current of up to “k×i” is supplied to the organic EL element50. When k=2, for example, even when one second TFT 20 does not operateat all in one pixel in the worst case, compared to the total current“2×i” which are supposed to be supplied to the organic EL element 50 inother pixels, supply of current i to the organic EL element 50 can beassured in this pixel by the other second TFT 20. When only a singlesecond TFT 20 is used, however, the current value becomes “0”,indicating a pixel defect, if the one TFT 20 is inoperative as in thecase described above. By providing a plurality of second TFTs as shownin FIG. 5A, a variation of the emission intensity of each organic ELelement 50 among different pixels can be reduced and a possibility ofpixel defect can be remarkably decreased, which contributes toaccomplishment of a circuit configuration with enhanced reliability.

The circuit configuration shown in FIG. 5B differs from that in FIG. 2in that the gate of the third TFT 30, along with the gate of the firstTFT 10, is connected to the gate line GL, and these gates are controlledby the same gate signal G. Although a change in the potential held onthe storage capacitor Cs can be reduced further reliably when the ONperiod of the third TFT 30 is set longer than that of the first TFT 10as shown in FIG. 4, even with a circuit configuration shown in FIG. 5Bin which ON/OFF control for both the first TFT 10 and the third TFT 30is performed at the same timing, it is unlikely that the third TFT 30turns OFF before the first TFT 10 turns OFF. It is therefore possible toaccumulate a charge in accordance with a data signal accurately in thestorage capacitor Cs for driving the second TFT 20. Further, the circuitconfiguration of FIG. 5B can minimize a layout space for the variouslines and the third TFT 30 within one pixel, as will be described withreference to FIG. 8. Consequently, the layout region for the organic ELelement 50 (the emission region), that is an aperture ratio, is alsoincreased compared to the configurations shown in FIGS. 2 and 5A. Itshould be noted that a plurality of the second TFTs 20 may be providedin the circuit configuration of FIG. 5B, as in the case of configurationshown in FIG. 5A.

FIG. 6 is a plan view showing an example configuration corresponding toone pixel having the circuit configuration shown in FIG. 5A. FIG. 7A isa cross section of the first TFT 10 taken along line A-A of FIG. 6. FIG.7B is a cross section of the second TFT 20 taken along line B-B of FIG.6. FIG. 7C is a cross section of the third TFT 30 taken along line C-Cof FIG. 6.

In the configuration of FIG. 6 which corresponds to that in FIG. 5A,each pixel comprises an organic EL element 50, first, second, and thirdTFTs 10, 20, and 30, respectively, and a storage capacitor Cs within apixel region. In the example shown in FIG. 6, the gate line (GL) 40extends in the row direction, and two gate electrodes 2 extend from thisgate line 40 above a region for forming an active layer 6 of the TFT 10,to form a double-gate type TFT. Further, the reset line (RSL) 46 fordriving the third TFT 30 is formed so as to extend in the row directionin parallel with the gate line 40, and a gate electrode 32 extends fromthis reset line 46 above the active layer 36 of the third TFT 30.

Further, the data line (DL) 42 for supplying a data signal to the firstTFT 10 and the drive power source line (VL) 44 for supplying a currentfrom the drive power source Pvdd to the second TFT 20 are disposed so asto extend in the column direction of the pixels. In addition, thecapacitor line (SL) 48 for supplying a fixed potential Vsl to the secondelectrode 8 of the storage capacitor Cs via the third TFT 30 (the drainof the TFT 30 in this example) is disposed in the column direction inparallel with the data line 42 and the drive power source line 44.

Further, two second TFTs 20 are connected in parallel between the drivepower source line 44 and the organic EL element 50. These two secondTFTs 20 are arranged in a straight line in such a manner that thechannel length direction of each TFT 20 is aligned with the columndirection (which corresponds to the longitudinal direction of the pixeland also with the extending direction of the data line 42 and the drivepower source line 44), and the common gate electrode 24 for these TFTs20 is extracted from the contact portion of the TFT 20 and the firstelectrode 7 of the storage capacitor Cs so as to extend above the activelayer 16 of the second TFT 20. Although the second TFT 20 is not limitedto such a layout, with the above arrangement in which the direction ofchannel length of TFT 20 corresponds to the longitudinal direction ofthe pixels, it is possible to effectively dispose the second TFT 20within a limited region of one pixel, when extension of the channellength of the second TFT 20 is desired so as to increase reliability.Further, as will be described below, in a case where poly-crystallinesilicon obtained by poly-crystallization of amorphous silicon by laserannealing is used as the active layer 16, if the scanning direction oflaser annealing is set to the column direction and a configuration isemployed in which two second TFTs 20 are arranged in the columndirection with a gap therebetween such that the extended channel lengthis oriented in the column direction as shown in FIG. 6, it is possibleto increase the possibility that the active layer 16 of each TFT 20 isirradiated with pulse laser a plurality of times to average a difference(reduce the difference) in characteristics of TFTs 20 among differentpixels.

The cross sectional configuration of each circuit element of one pixelwill be described, with further reference to FIGS. 7A to 7C. As shown inFIGS. 7A to 7C, according to the present embodiment, all the first,second and third TFTs 10, 20 and 30 adopt the so-called top gate TFTconfiguration in which the gate electrode (2, 24, 32) is formed abovethe active layer (6, 16, 36) with a gate insulating film 4 interposedtherebetween. (The bottom-gate type may, of course, also be adopted.)

The respective active layers 6, 16, 36 of the first, second, third TFTs10, 20, 30, respectively, are formed on a transparent insulatingsubstrate 1 such as glass, by poly-crystallizing an a-Si layer using thelaser annealing process commonly performed for all these TFTs and thenpatterning p-Si obtained by the laser annealing. In the active layers ofall the TFTs, n-type impurities are doped in the source and drainregions using the common doping process, and all the TFTs are thusconfigured as an n-ch TFT.

The first TFT 10, in which the gate electrodes 2 are protruded from thegate line 40 at two different positions, is formed as a double gate typeTFT in term of circuit configuration. The active layer 6 includes anintrinsic channel region 6 c in which no impurities are doped,immediately under each gate electrode 2, and the drain region 6 d andthe source region 6 s in which impurities such as phosphorus are dopedon either sides of the channel region 6 c, so as to form an n-ch TFT.

The drain region 6 d of the first TFT 10 is connected to the data line42 formed on an inter-layer insulating film 14 extending so as to coverthe first TFT 10 entirely for supplying a data signal of a colorcorresponding to the pixel, via a contact hole formed through theopening of the interlayer insulating film 14 and the gate insulatingfilm 4.

The source region 6 s of the first TFT 10 also serves as the firstelectrode 7 of the storage capacitor Cs. The second electrode 8 made ofthe same material as that of the gate line 40 or the like is formedabove the first electrode 7 with the gate insulating film 4 interposedtherebetween, and a region in which the first and second electrodes 7and 8 overlap with each other having the gate insulating film 4interposed therebetween constitutes the storage capacitor Cs. The firstelectrode 7 extends into the region where the second TFT 20 is formed(the active layer 16) and is connected with the gate electrode 24 of thesecond TFT 20 through a connection line 26. The second electrode 8 isconnected with the drain 36 d of the third TFT 30, the source 16 s ofthe second TFT 20, and an anode 52 of the organic EL element 50 whichwill be described below, through a common connection line 34 which isformed simultaneously with the data line 42 or the like, also describedbelow, in a layer above the inter-layer insulating film 14 which isformed as so to cover the second electrode 8, the gate electrode 2, andthe gate line 40.

The active layer 16 of two second TFTs 20 includes an intrinsic channelregion 16 c immediately under the gate electrode 24, and the drainregion 16 d and the source region 16 s in which impurities such asphosphorus are doped on either side of the channel region 16 c, so as toform an n-ch TFT. In the example shown in FIGS. 6 and 7B, the drainregion 16 d is common for the two second TFTs 20, and is connected, viaa single common contact hole formed through the opening of theinter-layer insulating film 14 and the gate insulating film 4, with thedrive power source line 44 which also serves as the drain electrode. Thesource region 16 s of each of the two second TFTs 20, on the other hand,is connected to the common connection line 34 via a contact hole formedin the opening in the inter-layer insulating film 14 and the gateinsulating film 4.

The third TFT 30 also has a configuration basically similar to theconfigurations of the first and second TFTs 10 and 20, and includes achannel region 36 c under the gate electrode 32 which is integral withthe reset line (RSL) 46, and source region 36 s and drain region 36 d inwhich impurities such as phosphorus are doped on either side of thechannel region 36 c, so as to form an n-ch TFT.

The source region 36 s of the third TFT 30 is connected to the capacitorline (SL), which also serves as a source electrode, via a contact holeformed through the opening of the inter-layer insulating film 14 and thegate insulating film 4. The drain region 36 d of the third TFT 30 isconnected to the common connection line 34, which also serves as a drainelectrode, via a contact hole formed through the opening of theinter-layer insulating film 14 and the gate insulating film 4.

Each of the gate electrodes 2 of the first TFT 10 (the gate line 40),the gate electrodes 24 (including the line portion from the connectionline 26) of the second TFT 20, the gate electrode 32 of the third TFT 30(the reset line 46), and the second electrode 8 of the storage capacitorCs is simultaneously formed by patterning using Cr, for example.Further, each of the data line 42, the drive power source line 44, thecapacitor line 48, the common connection line 34, and the connectionline 26 is simultaneously formed by patterning using Al, for example. Asshown in FIG. 6, the common connection line 34 connected to the sourceregion 16 s of the second TFT 20 is provided along the longitudinaldirection of the pixel (in the column direction in this example) so asto cover the region between the anode 52 of the organic EL element 50,which will be described later, and the gate electrode forming region ofthe second TFT 20. Therefore, the common connection line 34 canaccomplish the function of interrupting light emitted from the organicEL element 50 toward the glass substrate 1.

The common connection line 34 connected with the source region 36 s ofthe third TFT 30, the second electrode 8 of the storage capacitor Cs,and the source region 16 s of the second TFT 20, is in turn connectedwith the anode 52 of the organic EL element 50 via a contact hole formedthrough the opening of a first planarizaion insulating film 18 which isformed so as to cover the entire substrate including the connection line34, the data line 42, the drive power source line 44, and the capacitorline 48, as shown in FIG. 7B.

According to the present embodiment, three types of TFTs, the first,second, and third TFTs 10, 20, and 30 are formed within each pixel, asdescribed above. In this case, with the circuit configuration whichallows the use of an n-ch TFT as the second TFT 20, it is possible toform these three types of TFTs 10, 20, and 30 simultaneously through thesame process, which then prevents an increase in the number of processsteps as would otherwise result when the number of TFTs is increased.

The organic EL element 50 is formed by the transparent anode 52 made ofITO (Indium Tin Oxide) or the like, a cathode 57 made of a metal such asAl, and an emissive element layer (organic layer) 51 made of an organiccompound disposed between the anode 52 and the cathode 57. In thisembodiment, the anode 52, the emissive element layer 51, and the cathode57 are sequentially formed in that order from the side of the substrate1 as shown in FIG. 7B. Further, referring to FIG. 7B, on the firstplanarization insulating layer 18, a second planarization insulatinglayer 61 having an opening only at a center region where the anode 52 ofthe organic EL element 50 is formed is provided so as to cover the edgeportion of the anode 52, the line region, the first, second and thirdTFT forming regions, and the storage capacitor forming region, so thatshort circuit of the anode 52 and the cathode 57 which is the upper mostlayer and disconnection of the emissive element layer 51 can beprevented.

The emissive element layer 51, in this example, is formed bysequentially accumulating, from the anode side for example, a holetransport layer 54, an organic emissive layer 55, and an electrontransport layer 56 in a laminate structure by vapor deposition or thelike. In the case of a color display apparatus in which each pixel isassigned to a different color of R (red), G (green), or B (blue), forexample, the emissive layer 55 is made of a different materialcorresponding to the assigned color. The remaining hole transport layer54 and the electron transport layer 56 may be formed as common layersfor all the pixels as illustrated in FIG. 7B, or may be formed by adifferent material for each color similar to the emissive layer 55.Example material used for each layer is as follows.

Hole transport layer 54: NBP

Emissive layer: for red (R) . . . doping a dopant of red color (DCJTB)into a host material (Alq₃)

-   -   for green (G) . . . doping a dopant of green color        (Coumarin 6) into a host material (Alq₃)    -   for blue (B) . . . doping a dopant of blue color        (Perylen) into a host material (Alq₃)

Electron transport layer 56: Alq₃

An electron injecting layer made of lithium fluoride (LiF) may befurther formed between the cathode 57 and the electron transport layer56. Further, the hole transport layer 54 may be formed by first andsecond hole transport layers made of different materials. Also, althougheach emissive element layer 51 must include the emissive layer 55including at least an emissive material, the hole transport layer 54 andthe electron transport layer 56 or the like described above is notnecessarily required depending on a material used for that layer.

The abbreviations used in the above description refer to the followingmaterials:

-   -   “NBP” refers to        N,N′-di((naphthalene-1-yl)-N,N′-diphenyl-benzidine);    -   “Alq₃” refers to tris(8-hydroxyquinolinato)aluminum;    -   “DCJTB” refers to        (2-(1,1-dimethylethyl)-6-(2-(2,3,6,7-tetrahydro-1,1,7,7-tetramethyl-1H,5H-benzo[ij]quinolizin-9-yl)ethenyl)-4H-pyran-4-ylidene)propanedinitrile;        and    -   “Coumarin 6” refers to        3-(2-benzothiazolyl)-7-(diethylamino)coumarin.

It should be noted that the configuration and the materials for theemissive element layer 51 are not limited to those described above.

Another pixel configuration according to the embodiment of the presentinvention will be described with reference to FIG. 8. FIG. 8 shows anexemplary plan view corresponding to one pixel having the circuitconfiguration shown in FIG. 5B, in which parts similar to those in FIGS.6 and 7 are denoted by the same numerals. The plan configuration shownin FIG. 8 differs from that in FIG. 6 mainly in that the gate line 41which also serves as the gate electrode 2 of the first TFT 10 forsupplying a gate signal G also acts as the gate electrode 32 of thethird TFT 30, and in that a single second TFT 20 is provided between thedrive power source line 44 and the anode 52 of the organic EL element50. The cross sectional configuration of each TFT 10, 20, 30, thestorage capacitor Cs, and the organic EL element 50 is substantiallysimilar to those shown in FIGS. 7A to 7C. Of course, in theconfiguration of FIG. 8, the second TFT 20 is also of an n-ch TFTstructure, and the gate-source voltage is maintained by the storagecapacitor Cs at a voltage in accordance with a data signal.

In the example configuration of FIG. 8, by using the gate line 41 alsoas the gate electrode 2 of the first TFT 10 and the gate electrode 32 ofthe third TFT 30, only one gate line 41 is provided for each row as aline extending in the column direction, so that each pixel formingregion can be increased accordingly compared to the configuration ofFIG. 6. In the example of FIG. 8, the active layer 36 of the third TFT30 is disposed in parallel with the active layer 6 of the first TFT 10at the position more distant from the gate line 41 than the active layer6. The data line 42 for supplying a data signal to the first TFT 10crosses over the active layer 36 of the third TFT 30. The drain side ofthe third TFT 30 is connected to the capacitor line 48 which extends inthe column direction in parallel with the data line 42. The drain region36 d of the third TFT 30 is connected, via the common connection line34, with each of the second electrode 8 of the storage capacitor Csdisposed along the longitudinal direction of the drive power source lien44 in FIG. 8, the source region 16 s of the second TFT 20, and the anode52 of the organic EL element 50.

As is obvious from a comparison of FIGS. 6 and 8, assuming that thepitch of disposing the drive power source line 44 in the row directionis substantially the same in both configurations, the configuration ofFIG. 8 can secure a larger area within one pixel for forming the anode52 of the organic EL element 50, so that a higher aperture ratio, whichis synonymous with display at a higher brightness, can be accomplished.

Although in the above examples, poly-crystalline silicon (p-Si) is usedfor the active layer of each of the first to third TFTs 10, 20 and 30,amorphous silicon (a-Si) may, of course, be used for the active layer.When a TFT including an active layer formed by p-Si is employed, TFTs inwhich the same p-Si is used for the active layers are formed in theabove-described vertical and horizontal drivers for driving each pixelon the same substrate. In such a case, because the TFT of the driversection often adopts a CMOS structure, it is necessary to form both n-chand p-ch TFTs. When a-Si is used for the TFT of each pixel, on the otherhand, a dedicated IC is externally provided as a driver for driving eachpixel. According to the present invention, because all of the threetypes of TFTs formed within one pixel can be configured as an n-ch TFT,it is possible to simplify the manufacturing process compared to a casewhere a p-ch TFT is used as the second TFT 20.

Further, in each TFT, an LD (Lightly Doped) region may be formed asnecessary between the channel and drain regions or between the channeland source regions.

A still further use of the resetting third TFT 30 provided in each pixelin accordance with the present embodiment will be described. During thenormal display period, in order to cause the storage capacitor Cs tohold the gate-source voltage of the second TFT 20, the third TFT 30 iscontrolled ON or OFF at the same timing as the first TFT 10 as describedabove. However, the third TFT 30 can be used for another use duringanother period.

Specifically, the third TFT 30 can be used for forcing the chargesaccumulated between the anode and the cathode of the organic EL element50 to be discharged at the predetermined timing. During a period inwhich the gate-source voltage Vgs of the second TFT 20 is maintained atthe predetermined level by the storage capacitor Cs, a current inaccordance with the voltage Vgs continuously flows between the anode 52and the cathode 57 of the organic EL element 50 and when the displayperiod of the pixel is completed, a certain degree of charges remainbetween the anode and the cathode. Such a remaining charge would affectthe display content of that pixel at the following display period, andmay result in a phenomenon such as image retention. Therefore, byturning the third TFTs 30 of all the pixels ON simultaneously orsequentially at predetermined periods, such as once per verticalscanning period, in the blanking period, for example, it is possible toconnect the anode 52 of the organic EL element 50 with the capacitorline 48 to make the anode potential at the potential of the capacitorline 48, that is 0V, for example. Under such a control, chargesremaining in the organic EL element 5 b can be discharged through thethird TFT 30 after completion of one display period and before the startof the following display period, so that high quality display free fromimage retention or the like can be achieved. Further, becausecharacteristics deterioration in the organic EL element 50 tends toaccelerate as a greater amount of current flows therethrough, removal ofunnecessary charge can prevent unnecessary current from continuouslyflowing through the organic EL element 50, thereby extending the life ofthe organic EL element 50.

For another usage, the third TFT 30 can also be used for inspection ofeach pixel before shipment from a factory, for example. Specifically,when a data signal for inspection is written while the first TFT 10 isturned ON and the second TFT 20 is then turned ON, a current inaccordance with the written inspection data flows from the drive powersource line 44 to drain-source of the second TFT 20, and the sourcevoltage of the second TFT 20 should be a voltage in accordance with acurrent amount supplied to the organic EL element 50. At this time, itis possible to control the third TFT 300N to thereby reliably and simplyinspect whether or not the source voltage (or a current flowing throughthe source) of the second TFT 20 can supply an appropriate current tothe organic EL element 50 by means of voltage measurement or the like ofthe capacitor line 48.

Another configuration of the second TFT 20 will be described withreference to FIG. 9. The exemplary configuration of the second TFT 20shown in FIG. 9 differs from that in FIG. 7 in that the second TFT 20 isconfigured as a so-called LDD type TFT having a lightly doped (LD)region (typically referred to as LDD regions). In this example, thesecond TFT 20 has a general single-gate structure, in which LD regions16LDs are provided. More specifically, on the glass substrate 1, theactive layer 16 is formed and the gate insulating film 4 is furtherformed so as to cover the active layer 16. On the gate insulating film 4at the portion corresponding to the center portion of the active layer16, the gate electrode 24 is provided.

Further, at either edge of the active layer 16, the drain region 16 dand the source region 16 s in which impurities are doped at a highconcentration are provided. The portion of the active layer 16 under thegate electrode 24 is the channel region 16 c, and a portion between thechannel region 16 c and the source region 16 s and a portion between thechannel region 16 c and the drain region 16 d are LD regions 16LD inwhich a low concentration of impurities is doped.

When a TFT having larger LD regions compared to the peripheraltransistors is used as the second TFT 20, it is possible to increaseresistance to high voltage and increase the current amount change withrespect to the gate voltage change.

Specifically, when the gate length (in the channel length direction) ofthe TFT 20 is increased, the range in which a current amount changeswith respect to the gate voltage can be increased to thereby improve theaccuracy of current amount adjustment using a change in the gatevoltage. According to the present embodiment, the large LD configurationcan accomplish the same effect as such an increased gate length.

When the width of the gate electrode 24 is actually increased toincrease the gate length of TFT, it is necessary to wire such a gateelectrode 24 having a wide width (having a long gate length) whileinsulation between the gate electrode 24 and other elements are secured.According to the present invention, however, as the LD configuration canprovide substantially the same effect as increasing the gate length, itis not necessary to increase the width of the light shielding gateelectrode 24, and the aperture ratio in one pixel can therefore beimproved.

Such an LD configuration may be employed for the first TFT 10 and theTFT of driver circuits.

According to the present embodiment, the LD region of the second TFT 20is made larger than that of the first TFT 10 and the TFT of drivercircuits.

Specifically, assume that the LD region of the first TFT 10 or the TFTin driver circuits has a length as shown in FIG. 9, the LD region of thesecond TFT 20 is made larger as shown in FIG. 10. Consequently, theamount of current can be controlled more accurately withoutsubstantially changing the size of the transistor itself. Further, useof a gate electrode having a width similar to that of the gate electrodeof other TFTs such as the TFT 10 in the second TFT 20 can facilitate theTFT design.

As described above, because in this LD configuration the gate electrode24 need not have a large width, the aperture ratio can be increased.Consequently, the emission area per pixel can be increased to therebyincrease brightness without changing the amount of current flowingthrough each organic EL element. On the contrary, due to the increasedaperture ratio, the same brightness can be accomplished with a reducedamount of current supplied to the organic EL element, so thatdeterioration of the organic EL element can be reduced. Further, becausethe gate length, namely the channel length (including the LD region),can be substantially increased, a variation in characteristics withregard to re-crystallization (poly-siliconization) of the active layerby means of eximer laser annealing can be reduced.

Referring to FIG. 11, a circuit configuration in accordance with anotherembodiment of the present invention will be described. When compared tothe circuit shown in FIG. 2, the circuit of FIG. 11 further includes adiode 31 used for voltage adjustment. More specifically, the diode 31 isprovided between the storage capacitor Cs and the third TFT (dischargingtransistor) 30 and the organic EL element 50. The diode 31 is formed byshort-circuit of gate-drain of a TFT having the same configuration asthe second TFT 20.

Because this diode 31 is provided, the gate voltage of the second TFT 20can be set at a sum of the threshold (VtF) of the organic EL element 50,the threshold (Vtn) of the diode 51, and a video signal. It is thereforepossible to cause the second TFT 20 to always flow a currentcorresponding to the video signal regardless of a difference ordeterioration of thresholds of the organic EL element 50 and the TFTtransistors.

In other words, provision of the diode 31 permits control of a drivingcurrent substantially independent from variation or deterioration ofelement characteristics, so that a display apparatus with less colorirregularity can be provided.

Further, in the circuit shown in FIG. 11, the third TFT 30 is providedfor setting the anode side potential of the organic EL element 50 at thevoltage of the capacitor line SL which is a ground potential to therebyperform initial setting when driving the organic EL element 50. Byforcing the anode side potential of the organic EL element 50 to acertain potential (by extracting charges) as described above, the imageretention phenomenon can be reduced. In addition, by setting the sourceside potential of the third TFT 30 at a potential which is further lowerthan the cathode side potential of the organic EL element, it ispossible to reversely bias an organic film including at least an organicemissive film in the organic EL element. Recovery of characteristics ofthe organic film are thereby accelerated and deterioration of the filmcharacteristics is delayed.

Further, because the third TFT 30 is provided in each pixel, it ispossible to activate the reset line RSL of all the pixels connected inthe gate line direction to thereby control non-emission time. Thispermits brightness adjustment and also achieves low power consumption.Further, by connecting the reset lines RSL for each of RGB and varyingthe ON time for each of RGB, the emission time for each of RGB can becontrolled, so that adjustment of white balance and prevention of imagedeterioration can be accomplished.

FIG. 12 shows another exemplary configuration in which the gate of thethird TFT 30 shown in FIG. 11 is connected to the gate line GL, not tothe reset line RSL. This configuration can also provides the operationaleffect similar to the case of FIG. 11. More specifically, when the gateline GL is activated, the first TFT 10 is turned ON, and the gatevoltage of the second TFT 20 is set at the voltage of the data line DL.Also, because the third TFT 30 is turned ON, a current flows from thepower source line VL to the capacitor line SL at the low voltage (groundpotential) via the second and third TFTs 20 and 30.

Then, deactivation of the data line DL turns the first and third TFTs 10and 30 OFF and causes a current from the second TFT 20 to flow throughthe organic EL element 50 which then emits light.

At this point, the potential on the upper side (the side connected tothe second TFT 20) of the organic EL element 50 is at a voltage higherthan the voltage drop VtF at the diode 31. On the other hand, due toexistence of the voltage drop Vtn at the diode 31, the gate voltage ofthe second TFT 20 corresponds to the sum of the threshold (VtF) of theorganic EL element 50, the threshold (Vtn) of the diode 31 and thevoltage of a video signal (Vvideo) when a current is flowing through theorganic EL element 50. Accordingly, it is possible to control a drivingcurrent substantially independent from variation or deterioration ofelement characteristics, so that a display apparatus with less colorirregularity can be provided, as described above.

While the preferred embodiments of the present invention have beendescribed using specific terms, such description is for illustrativepurposes only, and it is to be understood that changes and variationsmay be made without departing from the spirit or scope of the appendedclaims.

1-22. (canceled)
 23. A display apparatus including a plurality ofelectroluminescence elements arranged in a matrix, wherein a drivingtransistor is provided corresponding to each electroluminescence elementfor controlling a drive current to be supplied to theelectroluminescence element, and the driving transistor is an n-channeltransistor and includes an LD region in which a low concentration ofimpurities is doped, between a channel region and each of source anddrain regions in which a high concentration of impurities is doped. 24.(canceled)
 25. A display apparatus including a plurality ofelectroluminescence elements arranged in a matrix, wherein a drivingtransistor is provided corresponding to each electroluminescence elementfor controlling a drive current to be supplied to theelectroluminescence element, the driving transistor is an n-channeltransistor and includes an LD region in which a low concentration ofimpurities are doped, between a channel region and each of source anddrain regions in which a high concentration of impurities are doped, andthe LD region of the driving transistor is made larger than an LD regionof an n-channel transistor at least in a peripheral circuit.